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this is information on a product in full production. november 2012 doc id 023992 rev 1 1/59 59 L6751 digitally controlled dual pwm for intel vr12 and amd svi datasheet ? production data features vr12 compliant with 25 mhz svid bus rev. 1.5 ? serialvid with programmable imax, tmax, vboot, address amd svi compliant second generation ltb technology ? flexible driver/drmos support jmode support fully configurable through pmbus ? dual controller: ? up to 6 phases for core and memory ? 1 phase for graphics (gfx), system agent (vsa) or northbridge (vddnb) single ntc design for tm, ll and imon thermal compensation (for each section) vfde and gdc - gate drive control for efficiency optimization dpm - dynamic phase management dual remote sense; 0.5% vout accuracy full-differential current sense across dcr avp - adaptive voltage positioning dual independent adjustable oscillator dual current monitor pre-biased output management average and per-phase oc protection ov, uv and fb disconnection protection dual vr_rdy wlpga72 6x6 mm package applications high-current vrm / vrd for desktop / server / workstation intel ? / amd cpus ddr3 memory supply description the L6751 is a universal digitally controlled dual pwm dc-dc designed to power intel?s vr12 and amd svi processors and memories: all required parameters are programmable through dedicated pinstrapping and pmbus interface. the device features up to 6-phase programmable operation for multi-phase sections and a single-phase with independent control loops. when configured for memory supply, single-phase (vtt) reference is always tracking multi-phase (vddq) scaled by a factor of 2. the L6751 supports power state transitions featuring vfde, programmable dpm and gdc maintaining the best efficiency over all loading conditions without compromising transient response. the device assures fast and independent protection against load overcurrent, under/overvoltage and feedback disconnections. the device is available in wlpga72 6x6 mm package. table 1. device summary order code package packaging L6751 wplga72 6x6 mm tray L6751tr wplga72 6x 6mm tape and reel wplga72 6x6 mm www.st.com
contents L6751 2/59 doc id 023992 rev 1 contents 1 typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 5 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 device configuration and pinstrapping tables . . . . . . . . . . . . . . . . . . . 21 4.1 jmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 programming hiz level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 multi-phase section - phase # programming . . . . . . . . . . . . . . . . . . . . . . 30 6.2 multi-phase section - current reading and current sharing loop . . . . . . . . 30 6.3 multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 single-phase section - disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5 single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6 single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 dynamic vid transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 lsless startup and pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.8 dvid optimization: ref/sref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 36 7.1 overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 overcurrent and current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.1 multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
L6751 contents doc id 023992 rev 1 3/59 7.2.2 overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.3 single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 single ntc thermal monitor and compensation . . . . . . . . . . . . . . . . . 41 8.1 thermal monitor and vr_hot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 tm/stm and tcomp/stcomp design . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 dynamic phase management (dpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 variable frequency diode emulation (vfde) . . . . . . . . . . . . . . . . . . . . . . 44 9.2.1 vfde and drmos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 gate drive control (gdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 system control loop compensati on . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1 compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 ltb technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 pmbus support (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 enabling the device through pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.2 controlling vout through pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3 input voltage monitoring (read_vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.4 duty cycle monitoring (read_duty) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.5 output voltage monitoring (read_vout) . . . . . . . . . . . . . . . . . . . . . . . . 55 12.6 output current monitoring (read_iout) . . . . . . . . . . . . . . . . . . . . . . . . 55 12.7 temperature monitoring (read_temperature) . . . . . . . . . . . . . . . . . 55 12.8 overvoltage threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
list of tables L6751 4/59 doc id 023992 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. phase number programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. imax, simax pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. addr pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. boot / tmax pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. dpm pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. gdc threshold definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. L6751 protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. multi-phase section oc scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15. efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 17. ov threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18. L6751 wplga72 6x6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
L6751 list of figures doc id 023992 rev 1 5/59 list of figures figure 1. typical 6-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. L6751 pin connections (left: top view - right: bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. jmode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5. device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7. current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. lsless startup: enabled (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. lsless startup: disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. dvid optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. output current vs. switching frequency in psk mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 13. efficiency performance with and without enhancements (dpm, gdc). . . . . . . . . . . . . . . . 45 figure 14. rosc vs. f sw per phase (r osc to gnd - left; r osc to 3.3 v - right) . . . . . . . . . . . . . . . . 46 figure 15. equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 16. control loop bode diagram and fine tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17. device initialization: pmbus controlling vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 18. L6751 wplga72 6x6 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
typical application circuit and block diagram L6751 6/59 doc id 023992 rev 1 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical 6-phase application circuit h s 1 l s 1 l1 c hf cdec r c boot ugate pha s e lgate pwm vcc l6747 en +12v rg h s 2 l s 2 l2 c hf r c boot ugate pha s e lgate vcc l6747 en +12v r g h s3 l s3 l 3 chf r c boot ugate pha s e lgate vcc l6747 en +12v rg h s 4 l s 4 l4 chf r c boot ugate pha s e lgate vcc l6747 en +12v rg s h s s l s s l chf boot ugate pha s e lgate pwm vcc l6747 en +12v r g s endrv s pwm s c s p s c s n c s 4n c s 4p pwm4 c s3 n c s3 p pwm 3 c s 2n c s 2p pwm2 c s 1n c s 1p pwm1 vr12 mp load uncore core vr12 s vid b u s c out c mlcc c s out c s mlcc gnd pwm gnd pwm gnd pwm gnd gnd cdec cdec cdec c dec vr12 s vid b u s s vclk alert# s vdata cf rf c i ri rfb cp rgnd v s en fb comp c ref r ref ref c s f r s f c s i r s i r s fb c s p s rgnd s v s en s fb s comp ltb endrv imax / s imax +12v vdrv boot / tmax addr o s c s o s c +5v vcc5 gdc gnd x2 (+pad) dpm1- 3 vrrdy s vrrdy vr_rdy s vr_rdy vr_hot vr_hot en en imon ilim dpm4-6 tm vcc5 ntc (nth s 0 8 05n02n6 8 01) (clo s e to the hot s pot) s t L6751 (6+1) reference s chem a tic h s 4 l s 4 l4 chf r c boot ugate pha s e lgate vcc l6747 en +12v r g pwm gnd cdec h s 4 l s 4 l4 c hf r c boot ugate pha s e lgate vcc l6747 en +12v r g pwm gnd c dec c s 4n c s 4p pwm4 c s 4n c s 4p pwm4 fbr s fbr s imon r imon rilim r s imon ro s c r s o s c s tm vcc5 ntc (nth s 0 8 05n02n6 8 01) (clo s e to the hot s pot) tcomp s tcomp c s ref r s ref s ref pmb us (tm) s mclk s mal# s mdata vin +12v pha s e pha s e1 L6751 am14 8 09v1
L6751 typical application circuit and block diagram doc id 023992 rev 1 7/59 1.2 block diagram figure 2. block diagram pwm4 pwm 3 pwm2 pwm1 pwm1 pwm2 pwm 3 pwm4 ltb technology mod u l a tor & fre qu ency limiter r a mp & clock gener a tor with vfde dpm control differenti a l c u rrent s en s e c u rrent b a l a nce & pe a k c u rr limit therm a l compen sa tion a nd g a in a dj us t c s 1p c s 1n c s 2p c s 2n c s3 p c s3 n c s 4p c s 4n lt b error amplifier tm tcomp vr_hot i lim i droop voc_tot vr12 b us m a n a ger & pin s tr a pping m a n a ger fb ref comp s vdata alert# s vclk ilim d ua l dac & ref gener a tor vr12 regi s ter s imax / s imax boot / tmax rgnd fbr ov +175mv m u ltiph as e f au lt m a n a ger oc s ref therm a l s en s or a nd monitor tempzone tempzone imon s imon ch a n # n ltb technology mod u l a tor & fre qu ency limiter r a mp & clock gener a tor withvfde s o s c s pwm / s en s pwm error amplifier voc_tot s fb s ref s comp s imon s ov +175mv s oc s ingleph as e f au lt m a n a ger vr_rdy flt flt to s ingleph as e flt m a n a ger to m u ltiph as e flt m a n a ge s vr_rdy s flt s flt s c s p s c s n s t a rt- u p logic & gdc control vdrv vcc5 gdc en s endrv endrv s _en en s _en gnd (pad) o s c v s en i ref i ref i s ref i s ref s tm s tcomp pwm5 pwm6 c s 5p c s 5n c s 6p c s 6n pmb us (tm) decodific a tion engine & control logic s mdata s mal# s mclk vin pha s e ch a n # v s en, s v s en vid, s vid pwm5 pwm6 dpm dpm dpm4-6 dpm1- 3 dpm addr i mon imon v s en remote buffer ref ref ref s rgnd s fbr s v s en s ref s ref L6751 am14 8 10v1
pin description and connection diagrams L6751 8/59 doc id 023992 rev 1 2 pin description and connection diagrams figure 3. L6751 pin connections (left: top view - right: bottom view) 2.1 pin description L6751 d1 a1 b1 a2 b2 a 3 b 3 a4 b4 a5 b5 a6 b6 a7 b7 a 8 b 8 a9 a10 b9 a11 b10 a12 b11 a1 3 b12 a14 b1 3 a15 b14 a16 b15 a17 b16 a1 8 a 3 6 b 3 2 a 3 5 b 3 1 a 3 4 b 3 0 a 33 b29 a 3 2 b2 8 a 3 1 b27 a 3 0 b26 a29 b25 a2 8 a27 b24 a26 b2 3 a25 b22 a24 b21 a2 3 b20 a22 b19 a21 b1 8 a20 b17 a19 d2 d 3 d4 pwm 3 pwm2 pwm1 pha s e nc vr_rdy gnd c s 6n c s 6p c s 5p c s 5n c s 4n c s 4p c s3 p c s3 n c s 2n c s 2p c s 1p c s 1n boot / tmax s v data alert# s vclk en nc vin o s c s tcomp s tm addr nc s mclk s mal# s mdata gnd imax/ s imax s comp vcc5 s o s c s ref tm s pwm s endrv ilim vr_hot tcomp s c s p s c s n s imon dpm4-6 s rgnd dpm1- 3 s fbr s v s en s fb pwm4 pwm5 pwm6 endrv s vr_rdy imon ref rgnd lt b fbr v s en fb comp nc vdrv nc gdc L6751 a9 b 8 d2 a10 b9 b16 a1 8 d 3 a19 b17 b24 a27 d4 a2 8 b25 b 3 2 a 3 6 d1 a1 b1 am14 8 11v1 table 2. pin description pin# name type function d1 pwm3 d (1) multi-phase section pwm output. connect to multi-phase channel 3 external driver pwm input. during normal operation the device is able to manage hiz status by setting and holding the pwmx pin to a fixed predefined voltage. see table 7 for phase number programming. a1 pwm2 d pwm output. connect to multi-phase external drivers pwm input. these pins are also used to configure hiz levels for compatibility with drivers and drmos. during normal operation the device is able to manage hiz status by setting and holding the pwmx pin to the predefined fixed voltage. b1 pwm1 d a2 phase a connect through resistor divider to multi-phase channel1 switching node. b2 nc - not internally bonded. a3 vr_rdy d vr ready. open drain output set free after ss has finished in multi-phase section and pulled low when triggering any protection on multi-phase section. pull up to a voltage lower than 3.3 v (typ.), if not used it can be left floating.
L6751 pin description and connection diagrams doc id 023992 rev 1 9/59 b3 gnd a gnd connection. all internal references and logic are referenced to this pin. filter to vcc5 with proper mlcc capacitor and connect to the pcb gnd plane. a4 cs6n a multi-phase section channel 6 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. when working at < 6 phases, still connect through rg to cs6p and then to the regulated voltage. filter the output-side of rg with 100 nf (typ) to gnd. b4 cs6p a channel 6 current sense positive input. connect through an r-c filter to the phase-side of the channel 6 inductor. when working at < 6 phases, short to the regulated voltage. a5 cs5p a channel 5 current sense positive input. connect through an r-c filter to the phase-side of the channel 5 inductor. when working at < 5 phases, short to the regulated voltage. b5 cs5n a channel 5 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. when working at < 5 phases, still connect through rg to cs5p and then to the regulated voltage. filter the output-side of rg with 100 nf (typ.) to gnd. a6 cs4n a channel 4 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. when working at < 4 phases, still connect through rg to cs4p and then to the regulated voltage. filter the output-side of rg with 100 nf (typ.) to gnd. b6 cs4p a multi-phase section channel 4 current sense positive input. connect through an r-c filter to the phase-side of the channel 4 inductor. when working at < 4 phases, short to the regulated voltage. a7 cs3p a channel 3 current sense positive input. connect through an r-c filter to the phase-side of the channel 3 inductor. when working at < 3 phases, short to the regulated voltage. b7 cs3n a channel 3 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. when working at < 3 phases, still connect through rg to cs3p and then to the regulated voltage. filter the output-side of rg with 100 nf (typ.) to gnd. a8 cs2n a channel 2 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output-side of rg with 100 nf (typ.) to gnd. b8 cs2p a channel 2 current sense positive input. connect through an r-c filter to the phase-side of the channel 2 inductor. a9 cs1p a channel 1 current sense positive input. connect through an r-c filter to the phase-side of the channel 1 inductor. d2 cs1n a channel 1 current sense negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output-side of rg with 100 nf (typ.) to gnd. table 2. pin description (continued) pin# name type function
pin description and connection diagrams L6751 10/59 doc id 023992 rev 1 a10 sosc a single-phase section oscillator pin. it allows the switching frequency f ssw to be programmed for the single-phase section. the pin is internally set to 1.02 v, frequency for single-phase is programmed according to the resistor connected to gnd or vcc with a gain of 11.5 khz/a. leaving the pin floating programs a switching frequency of 230 khz. see section 10 for details. b9 sref a the reference used for the single-phase section regulation is available on this pin with -125 mv offset. connect through an r sref -c sref to gnd to optimize dvid transitions. connect through r sos resistor to the sfb pin to implement small positive offset to the regulation. a11 tm a multi-phase section thermal monitor sensor. connect with proper network embedding ntc to the multi-phase power section. the ic senses the power section temperature and uses the information to define the vr_hot signal and temperature monitoring. by programming proper tcomp gain, the ic also implements load-line and imon/ilim thermal compensation for the multi-phase section. in jmode, the pin disables the single-phase section if shorted to gnd. pull up to vcc5 with 1 k to disable thermal sensor. see section 8 for details. b10 spwm / sen d single-phase section pwm output. connect to single-phase external driver pwm input. during normal operation the device is able to manage hiz status by setting and holding the pin to a fixed voltage defined by pwmx strapping. connect to vcc5 with 1 k to disable the single-phase section. a12 sendrv d single-phase section enable driver. cmos output driven high when the ic commands the driver. used in conjunction with the hiz window on the spwm pin to optimize the single- phase section overall efficiency. connect directly to external driver enable pin. b11 ilim a multi-phase section multi-phase section current limit. a current proportional to the multi-phase load current is sourced from this pin. connect through a resistor r lim to gnd. when the pin voltage reaches 2.5 v, the overcurrent protection is set and the ic latches. filter through c lim to gnd to delay oc intervention. a13 vr_hot d voltage regulator hot. open drain output, this is an alarm signal asserted by the controller when the temperature sensed through the st or tm pins exceed tmax (active low). see section 8 for details. b12 tcomp a thermal monitor sensor gain. connect proper resistor divider between vcc5 and gnd to define the gain to apply to the signal sensed by the tm to implement thermal compensation for the multi-phase section. short to gnd to disable temperature compensation (but not thermal sensor). see section 8 for details. table 2. pin description (continued) pin# name type function
L6751 pin description and connection diagrams doc id 023992 rev 1 11/59 a14 scsp a single-phase section single-phase section current senses positive input. connect through an r-c filter to the phase-side of the channel 1 inductor. b13 scsn a single-phase section current senses negative input. connect through an rg resistor to the output-side of the channel inductor. filter the output-side of rg with 100 nf (typ.) to gnd. a15 simon a current monitor output. a current proportional to the single-phase current is sourced from this pin. connect through a resistor r simon to gnd. when the pin voltage reaches 1.55 v, overcurrent protection is set and the ic latches. filtering through c simon to gnd allows the delay for oc intervention to be controlled. b14 dpm4-6 a pinstrapping connect a resistor divider to gnd/vcc5 in order to define the dpm and gdc strategies. see table 11 and ta b l e 1 2 for details. a16 srgnd a single-phase section remote buffer ground sense. connect to the negative side of the single-phase load to perform remote sense. b15 dpm1-3 a pinstrapping connect a resistor divider to gnd/vcc5 in order to define the dpm and gdc strategies. see table 11 and ta b l e 1 2 for details. a17 sfbr a single-phase section remote buffer positive sense. connect to the positive side of the single-phase load to perform remote sense. b16 svsen a remote buffer output. output voltage monitor, manages ov and uv protection. connect with a resistor r sfb // (r si - c si ) to sfb. a18 sfb a error amplifier inverting input. connect with a resistor r sfb // (r si - c si ) to svsen and with an (r sf - c sf )// c sh to scomp. d3 scomp a error amplifier output. connect with an (r sf - c sf )// c sh to sfb. the device cannot be disabled by pulling low this pin. a19 imax / simax a pinstrapping connect a resistor divider to gnd/vcc5 in order to define the imax and simax registers. see ta bl e 8 and table 6 for details. table 2. pin description (continued) pin# name type function
pin description and connection diagrams L6751 12/59 doc id 023992 rev 1 b17 gnd a gnd connection. all internal references and logic are referenced to this pin. filter to vcc5 with proper mlcc capacitor and connect to the pcb gnd plane. a20 smdata d pmbus pmbus data. b18 smal# d pmbus alert. a21 smclk d pmbus clock. b19 nc - not internally bonded. a22 addr a pinstrapping connect a resistor divider to gnd/vcc5 in order to configure the ic operating mode. see ta bl e 9 and ta bl e 6 for details. b20 stm a single-phase section thermal monitor sensor. connect with proper network embedding ntc to the single-phase power section. the ic senses the power section temperature and uses the information to define the vr_hot signal and temperature monitoring. by programming proper stcomp gain, the ic also implements load-line and simon thermal compensation for the single-phase section when applicable. short to gnd if not used. see section 8 for details. a23 stcomp a thermal monitor sensor gain. connect proper resistor divider between vcc5 and gnd to define the gain to apply to the signal sensed by st to implement thermal compensation for the single-phase section. short to gnd to disable temperature compensation. see section 8 for details. b21 osc a multi-phase section oscillator pin. it allows the programming of the switching frequency f sw for the multi-phase section. the pin is internally set to 1.02 v, frequency for multi-phase is programmed according to the resistor connected to gnd or vcc with a gain of 10 hz/a. leaving the pin floating programs a switching frequency of 200 hz per phase. effective frequency observable on the load results as being multiplied by the number of active phases n. see section 10 for details. a24 vin a input voltage monitor. connect to input voltage monitor point through a divider r vup / r vdwn to perform vin sense through pmbus (r up = 118.5 ; r down = 10 k typ.). b22 nc - not internally bonded. a25 en d level sensitive enable pin (3.3 v compatible). pull low to disable the device, pull up above the turn-on threshold to enable the controller. table 2. pin description (continued) pin# name type function
L6751 pin description and connection diagrams doc id 023992 rev 1 13/59 b23 svclk svc d svi bus serial clock. a26 alert# v_fix d alert (intel mode). v_fix (amd mode). pull to 3.3 v to enter v_fix mode. b24 svdata svd d serial data. a27 boot / tmax a pinstrapping connect a resistor divider to gnd/vcc5 in order to define boot and tmax registers. see ta bl e 1 0 for details. d4 vcc5 a main ic power supply. operative voltage is 5 v 5%. filter with 1 f mlcc to gnd (typ.). a28 gdc a gate drive control pin. used for efficiency optimization, see section 9 for details. if not used, it can be left floating. always filter with 1 f mlcc to gnd. b25 nc - not internally bonded. a29 vdrv a driving voltage for external drivers. connect to the selected voltage rail to drive external mosfet when in maximum power conditions. ic switches gdc voltage between vdrv and vcc5 to implement efficiency optimization according to selected strategies. b26 nc - not internally bonded. table 2. pin description (continued) pin# name type function
pin description and connection diagrams L6751 14/59 doc id 023992 rev 1 a30 comp / addr a multi-phase section error amplifier output. connect with an (r f - c f )// c p to fb. the device cannot be disabled by pulling low this pin. connect r comp = 12.5 k to gnd to extend pmbus addressing range (see ta bl e 9 ). b27 fb a error amplifier inverting input. connect with a resistor r fb // (r i - c i ) to vsen and with an (r f - c f )// c p to comp. a31 vsen a output voltage monitor, manages ov and uv protection. connect to the positive side of the load to perform remote sense. b28 fbr a remote buffer positive sense. connect to the positive side of the multi-phase load to perform remote sense. a32 ltb a ltb technology input pin. see section 11.2 for details. b29 rgnd a remote ground sense. connect to the negative side of the multi-phase load to perform remote sense. a33 ref a the reference used for the multi-phase section regulation is available on this pin with -125 mv offset. connect through an r ref -c ref to gnd to optimize dvid transitions. connect through r os resistor to fb pin to implement small positive offset to the regulation. b30 imon a current monitor output. a current proportional to the multi-phase load current is sourced from this pin. connect through a resistor r mon to gnd. the information available on this pin is used for the current reporting and dpm. the pin can be filtered through c imon to gnd. a34 svr_rdy (pwrok) d single-phase section vr ready (intel mode). open drain output set free after ss has finished and pulled low when triggering any protection for the single-phase section. pull up to a voltage lower than 3.3 v (typ.), if not used it can be left floating. powerok (amd mode). system-wide power good input. when low, the device decodes svc and svd to determine the boot voltage. b31 endrv d multi-phase section enable driver. cmos output driven high when the ic commands the drivers. used in conjunction with the hiz window on the pwmx pins to optimize the multi- phase section overall efficiency. connect directly to external driver enable pin. a35 pwm6 d multi-phase section pwm output. connect to related multi-phase channel external driver pwm input. during normal operation the device is able to manage hiz status by setting and holding the pwmx pin to fixed voltage defined before. see ta bl e 7 for phase number programming. b32 pwm5 d a36 pwm4 d pa d g n d a gnd connection. all internal references and logic are referenced to this pin. filter to vcc with proper mlcc capacitor and connect to the pcb gnd plane. 1. d = digital, a = analog. table 2. pin description (continued) pin# name type function
L6751 pin description and connection diagrams doc id 023992 rev 1 15/59 2.2 thermal data table 3. thermal data symbol parameter value unit r thja thermal resistance junction-to-ambient (device soldered on 2s2p pc board) 40 c/w r thjc thermal resistance junction-to-case 1 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c
electrical specifications L6751 16/59 doc id 023992 rev 1 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings 3.2 electrical characteristics (v cc5 = 5 v 5%, t j = 0 c to 70 c unless otherwise specified.) symbol parameter value unit vdrv, gdc to gnd -0.3 to 14 v vcc5, tm, stm, spwm, pwmx, sendrv, endrv, scomp, comp, smdata, smal#, smclk to gnd -0.3 to 7 v all other pins to gnd -0.3 to 3.6 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i vcc5 vcc5 supply current en = high 28 ma en = low 22 ma uvlo vcc5 vcc5 turn-on vcc5 rising 4.1 v vcc5 turn-off vcc5 falling 3 v uvlo vdrv vdrv turn-on vdrv rising 6.0 v vdrv turn-off vdrv falling 3 4.1 v uvlo vin vin turn-on vin rising, r up = 118.5 k ; r down = 10 k 6.0 v vin turn-off vin falling, r up = 118.5 k ; r down = 10 k 34.1v oscillator, soft-start and enable f sw main oscillator accuracy osc = open 170 200 230 khz oscillator adjustability r osc / r sosc = 47 k to gnd 378 420 462 khz f ssw main oscillator accuracy sosc = open 212 250 287 khz oscillator adjustability r osc / r sosc = 47 k to gnd 450 500 550 khz v osc pwm ramp amplitude (1) 1.5 v fault voltage at pin osc, ssosc latch active for related section 3 v
L6751 electrical specifications doc id 023992 rev 1 17/59 soft-start ss time - intel cpu mode vboot > 0, from pinstrapping; multi- phase section 5mv/ s vboot > 0, from pinstrapping; single- phase section 2.5 mv/ s vboot > 0, from pinstrapping; single- phase section, jmode on 2.5 mv/ s ss time - intel ddr mode vboot > 0, from pinstrapping; multi- phase section 2.5 mv/ s vboot > 0, from pinstrapping; single- phase section 1.25 mv/ s ss time - amd mode vboot > 0, from pinstrapping; both sections 6.25 mv/ s en tu r n - o n v en rising 0.6 v tu r n - o f f v en falling 0.4 v leakage current 1 a svi serial bus svclck, svdata input high 0.65 v input low 0.45 v svdata, alert# voltage low (ack) i sink = -5 ma 50 mv pmbus smdata, smclk input high 1.75 v input low 1.45 v smal# voltage low i sink = -4 ma 13 reference and dac k vid v out accuracy (mphase) i out = 0 a; n = 6; r g = 540 ; r fb = 1.108 k ; vid > 1.000 v -0.5 0.5 % k svid v out accuracy (sphase) i out = 0 a; r g = 1.3 k ; vid > 1.000 v -0.5 0.5 % i out = 0 a; r g = 1.3 k ; vid > 1.000 v; jmode = on -5 5 mv k vid , k svid v out accuracy vid = 0.8 v to 1 v -5 5 mv vid < 0.8 v -8 8 mv k vout v out accuracy - amd mode -20 20 mv droop ll accuracy (mphase) 0 to full load i infox = 0; n = 6; r g = 540 ; r fb = 1.108k -3 2 a same as above, i infox = 20 a-4.5 4.5 a table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specifications L6751 18/59 doc id 023992 rev 1 soft-start ss time - intel cpu mode vboot > 0, from pinstrapping; multi- phase section 5mv/ s vboot > 0, from pinstrapping; single- phase section 2.5 mv/ s vboot > 0, from pinstrapping; single- phase section, jmode on 2.5 mv/ s ss time - intel ddr mode vboot > 0, from pinstrapping; multi- phase section 2.5 mv/ s vboot > 0, from pinstrapping; single- phase section 1.25 mv/ s ss time - amd mode vboot > 0, from pinstrapping; both sections 6.25 mv/ s en tu r n - o n v en rising 0.6 v tu r n - o f f v en falling 0.4 v leakage current 1 a svi serial bus svclck, svdata input high 0.65 v input low 0.45 v svdata, alert# voltage low (ack) i sink = -5 ma 50 mv pmbus smdata, smclk input high 1.75 v input low 1.45 v smal# voltage low i sink = -4 ma 13 reference and dac k vid v out accuracy (mphase) i out = 0 a; n = 6; r g = 540 ; r fb = 1.108 k ; vid > 1.000 v -0.5 0.5 % k svid v out accuracy (sphase) i out = 0 a; r g = 1.3 k ; vid > 1.000 v -0.5 0.5 % i out = 0 a; r g = 1.3 k ; vid > 1.000 v; jmode = on -5 5 mv k vid , k svid v out accuracy vid = 0.8 v to 1 v -5 5 mv vid < 0.8 v -8 8 mv k vout v out accuracy - amd mode -20 20 mv droop ll accuracy (mphase) 0 to full load i infox = 0; n = 6; r g = 540 ; r fb = 1.108k -3 2 a same as above, i infox = 20 a-4.5 4.5 a table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L6751 electrical specifications doc id 023992 rev 1 19/59 sdroop ll accuracy (sphase) 0 to full load i scsn = 0; r g = 1.3 k -1.75 1 a i scsn = 20 a; r g = 1.3 k -1 1 a k imon imon accuracy (mphase) i infox = 0 a; n = 6; r g = 540 ; r fb = 1.108 k 00.75 a same as above, i infox = 20 a-4.5 4.5 a k simon simon accuracy (sphase) i scsn = 0 a; r g = 1.3 k 00.5 a i scsn = 20 a; r g = 1.3 k -1 1 a a 0 ea dc gain (1) 100 db sr slew rate (1) comp to sgnd = 10 pf 20 v/ s dvid - intel cpu mode slew rate fast multi-phase section 20 mv/ s slew rate slow 5 mv/ s slew rate fast single-phase section 10 slew rate slow 2.5 dvid - intel ddr mode slew rate fast multi-phase section 10 mv/ s slew rate slow 2.5 mv/ s dvid - amd mode slew rate both sections 5 mv/ s imon adc getreg(15h) v(imon) = 0.992 v cc hex accuracy c0 cf hex pwm outputs and endrv pwmx, spwm output high i = 1 ma 5 v output low i = -1 ma 0.2 v i pwm1 test current sourced from pin, en = 0. 10 a i pwm2 test current 0 a i pwmx, spwm test current sourced from pin, en = 0. -10 a endrv voltage low i endrv = -4 ma; both sections 0.4 v protection (both sections) ovp overvoltage protection vsen rising; wrt vid 100 200 mv uvp undervoltage protection vsen falling; wrt vid; vid > 500 mv -525 -375 mv fbr disc fb disconnection v cs- rising, above vsen/svsen 650 700 750 mv fbg disc fbg disconnection fbr input wrt vid 950 1000 1050 mv vr_rdy, svr_rdy voltage low i sink = -4 ma 0.4 v v oc_tot oc threshold, mphase v ilim rising, to gnd 2.5 v v soc_tot oc threshold, sphase v simon rising, to gnd 1.55 v table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specifications L6751 20/59 doc id 023992 rev 1 i oc_th constant current (1) mphase only 35 a vr_hot voltage low i sink = -4 ma 13 gate drive control gdc max. current any ps. 200 ma impedance ps00h (gdc=vcc12) 6 > ps00h; (gdc=vcc5) 6 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L6751 device configuration and pinstrapping tables doc id 023992 rev 1 21/59 4 device configuration and pinstrapping tables the L6751 features a universal serial data bus fully compliant with intel vr12/imvp7 protocol rev 1.5, document #456098 and amd svi specifications, document #40182. to guarantee proper device and cpu operation, refer to these documents for bus design, layout guidelines and any additional information required for the bus architecture. different platforms may require different pull-up impedance on the svi bus. impedance matching and spacing among svi bus lines must be followed. the controller configures itself automatically upon detection of different pinstrappings which are monitored at the ic power-up. see ta b l e 6 , 8 , 9 , 10 , and 11 for details. 4.1 jmode when enabled, multi-phase acts as if in ddr mode, while single-phase is an independent regulator with 0.75 v fixed reference (load-line disabled - tm can be used as enable for the single-phase). output voltage higher than the internal reference may be achieved by adding a proper resistor divider (ra, rb - see figure 4 ). to maintain precision in output voltage regulation, it is recommended to provide both sfbr and srgnd with the same divider. equation 1 figure 4. jmode: voltage positioning v out 0.750v ra rb + rb ----------------------- ? = 0.750v sfb scomp svsen sfbr r f c f r fb to vo u t (remote sense) protection monitor srgnd r a r a r b r b am14812v1
device configuration and pinstrapping tables L6751 22/59 doc id 023992 rev 1 4.2 programming hiz level the L6751 is able to manage different levels for hiz on pwmx guaranteeing flexibility in driving different external drivers as well as drmos ics. after en assertion and before soft-start, the device uses pwm1 and pwm2 to detect the driver/drmos connected in order to program the suitable hiz level of pwmx signals. during regulation, the hiz level is used to force the external mosfets in high impedance state. ? pwm1 sources a constant 10 a current, if its voltage results higher than 2.8 v, hiz level used during the regulation is 1.4 v, if lower, pwm2 information is used. ? pwm2 is kept in hiz, if its voltage results higher than 2 v, hiz level used during the regulation is 2 v, if lower, 1.6 v. an external resistor divider can be placed on pwm1 and pwm2 to force the detection of the correct hiz level. they must be designed considering the external driver/drmos selected and the hiz level requested. table 6. device configuration svi address droop (see table 8 ) imax / simax boot / tmax dpm vr12 0000b enabled. ta bl e 8 ta bl e 1 0 supported vr12 (1) () 0010b 0100b mphase: as per ta b l e 9 . sphase: disabled amd n/a mphase: enabled. sphase: as per ta bl e 9 . ignored tmax (2) supported 1. in ddr mode, single-phase reference is multi-phase vout/2 (jmode disabled). 2. refer to table 10 and choose any of the resistor combinations leading to the desired tnmax. other settings are ignored. table 7. phase number programming phase # pwm1 to pwm3 pwm4 pwm5 pwm6 3 to driver 1 k to vcc5 4 to driver 1 k to vcc5 5 to driver 1 k to vcc5 6 to driver
L6751 device configuration and pinstrapping tables doc id 023992 rev 1 23/59 table 8. imax, simax pinstrapping (1) rdown [k ] rup [k ] imax / simax imax [a] (2) simax [a] gfx vsa/ddr 10 1.5 40 29 10 2.7 35 21 22 6.8 30 13 10 3.6 25 5 27 11 40 29 12 5.6 35 21 82 43 30 13 13 7.5 25 5 56 36 40 29 18 13 35 21 15 12 30 13 18 16 25 5 15 14.7 40 29 10 11 35 21 18 22 30 13 56 75 25 5 10 15 40 29 12 20 35 21 12 22.6 30 13 39 82 25 5 47 110 40 29 10 27 35 21 22 68 30 13 10 36 25 5 18 75 40 29 15 75 35 21 10 59 30 13 10 75 25 5 10 100 40 29 10 150 35 21 10 220 30 13 10 open 25 5 n2556 + ? + ? + ? + ? + ? + ? + ? ?
device configuration and pinstrapping tables L6751 24/59 doc id 023992 rev 1 1. recommended values, divider needs to be connected between vcc5 pin and gnd. 2. n is the number of phase program med for the multi-phase section. table 9. addr pinstrapping (1) (2) rdown [k ] rup [k ] addr addr (3) pmbaddr (4) jmode droop multi-phase droop single-phase 10 1.5 amd mode cch n/a on on 10 2.7 off 22 6.8 c8h on 10 3.6 off 27 11 c4h on 12 5.6 off 82 43 c0h on 13 7.5 off 56 36 0100b (vr12) eeh n/a on off 18 13 off 15 12 eah on 18 16 off 15 14.7 e6h on 10 11 off 18 22 e2h on 56 75 off 10 15 0010b (vr12) ech n/a on off 12 20 off 12 22.6 e8h on 39 82 off 47 110 e4h on 10 27 off 22 68 e0h on 10 36 off
L6751 device configuration and pinstrapping tables doc id 023992 rev 1 25/59 . 18 75 0000b (vr12) cch / 8ch on on according to vboot settings (gfx / vsa) 15 75 off 10 59 c8h / 88h on 10 75 off 10 100 c4h / 84h on 10 150 off 10 220 c0h / 80h on 10 open off 1. recommended values, divider needs to be connected between vcc5 pin and gnd. 2. in ddr mode, when enabled, droop has 1/4th scaling factor. 3. svi address for multi-phase. single-phase is further offset by 0001b. in amd mode, svi address defaults according to amd specifications. 4. pmbus address for multi-phase (read/write). single-phas e is further offset by 02h. when in vr12 cpu mode, rcomp = 12.5 k to gnd, select between cxh (open) and 8xh (if installed) pmbus address. table 9. addr pinstrapping (1) (2) (continued) rdown [k ] rup [k ] addr addr (3) pmbaddr (4) jmode droop multi-phase droop single-phase table 10. boot / tmax pinstrapping (1) (2) rdown [k ] rup [k ] boot - intel address 0000b (3) intel address 0010b, 0100b (3) tmax [c] multi- phase single- phase link rest jmode vboot link rest 10 1.5 1.000 v 0.000 v vsa 32 sec (debug) on 1.500 v 32 sec (debug) 130 10 2.7 120 22 6.8 110 10 3.6 100 27 11 1.000 v 1.000 v vsa 32 sec (debug) 10 sec (functional) 130 12 5.6 120 82 43 110 13 7.5 100
device configuration and pinstrapping tables L6751 26/59 doc id 023992 rev 1 56 36 0.000 v 1.100 v vsa 10 sec (functional) on 1.350 v 32 sec (debug) 130 18 13 120 15 12 110 18 16 100 15 14.7 0.000 v 1.000 v vsa 10 sec (functional) 10 sec (functional) 130 10 11 120 18 22 110 56 75 100 10 15 0.000 v 0.900 v vsa 10 sec (functional) off 1.500 v 32 sec (debug) 130 12 20 120 12 22.6 110 39 82 100 47 110 0.000 v 1.000 v gfx 32 sec (debug) 10 sec (functional) 130 10 27 120 22 68 110 10 36 100 18 75 1.000 v 1.000 v gfx 32 sec (debug) off 1.350 v 32 sec (debug) 130 15 75 120 10 59 110 10 75 100 10 100 0.000 v 0.000 v gfx 10 sec (functional) 10 sec (functional) 130 10 150 120 10 220 110 10 open 100 1. recommended values, divider needs to be connected between vcc5 pin and gnd. 2. boot is ignored in amd mode, only tmax is operative. 3. operative mode defined by addr pin. see table 9 for details. table 10. boot / tmax pinstrapping (1) (2) (continued) rdown [k ] rup [k ] boot - intel address 0000b (3) intel address 0010b, 0100b (3) tmax [c] multi- phase single- phase link rest jmode vboot link rest
L6751 device configuration and pinstrapping tables doc id 023992 rev 1 27/59 table 11. dpm pinstrapping (1) 1. suggested values, divider needs to be connected between vcc5 pin and gnd. rdown [k ] rup [k ] dpm1-3 (2)(3) dpm4-6 (2)(3) dpm12 dpm23 gdc0 dpm34 dpm46 gdc1 10 1.5 16a +20a 1 +30a +22a 1 10 2.7 0 0 22 6.8 +16a 1 +14a 1 10 3.6 0 0 27 11 +10a 1 +8a 1 12 5.6 0 0 82 43 +6a 1 dpm off 1 13 7.5 0 0 56 36 12a +20a 1 +22a +22a 1 18 13 0 0 15 12 +16a 1 +14a 1 18 16 0 0 15 14.7 +10a 1 +8a 1 10 11 0 0 18 22 +6a 1 dpm off 1 56 75 0 0 10 15 8a +20a 1 +14a +22a 1 12 20 0 0 12 22.6 +16a 1 +14a 1 39 82 0 0 47 110 +10a 1 +8a 1 10 27 0 0 22 68 +6a 1 dpm off 1 10 36 0 0 18 75 off (12a) (4) +20a 1 +8a +22a 1 15 75 0 0 10 59 +16a 1 +14a 1 10 75 0 0 10 100 +10a 1 +8a 1 10 150 0 0 10 220 +6a 1 dpm off (5) 1 10 open 0 0
device configuration and pinstrapping tables L6751 28/59 doc id 023992 rev 1 2. transition threshold specified as delta with re spect to previous step (dpm23 is wrt dpm12). 3. gdc threshold is defined by combining gdc0 and gdc1 bits defined between the two different pinstrappings dpm1-3 and dpm4-6. see table 12 for details. 4. transition between 1phase and 2phase operation is set to 12 a but disabled in ps00h. 5. dynamic phase management disabled, ic always working at maximum possible number of phases except from when in >ps00h when transit ioning between 1phase and 2phase at 12 a. table 12. gdc threshold definition (1) gdc1 gdc0 threshold [a] (2) 1 1 0 0 1 0 gdc off 1. gdc threshold is defined by combining gdc0 and gdc1 bits defined between the two different pinstrappings dpm1-3 and dpm4-6. see table 11 for details. 2. n is the number of phase program med for the multi-phase section. n17a ? ? ?
L6751 device description and operation doc id 023992 rev 1 29/59 5 device description and operation the L6751 is a programmable 4/5/6-phase pwm controller that provides complete control logic and protection to realize a high performance step-down dc-dc voltage regulator optimized for advanced microprocessor and memory power supply. the device features 2 nd generation ltb technology: through a load transient detector, it is able to turn on simultaneously all the phases. this allows the output voltage deviation to be minimized and, in turn, the system cost to be minimized by providing the fastest response to a load transition. the L6751 implements current reading across the inductor in fully differential mode. a sense resistor in series to the inductor can also be considered to improve reading precision. the current information read corrects the pwm output in order to equalize the average current carried by each phase. the controller supports intel and amd svi bus and all the required registers. the platform may configure and program the defaults for the device through dedicated pinstrapping. a complete set of protections is available: overvoltage, undervoltage, overcurrent (per- phase and total), and feedback disconnection guarantees the load to be safe in all circumstances. special power management features like dpm, vfde (a) and gdc modify phase number, gate driving voltage and switching frequency to optimize efficiency over the load range. the L6751 is available in wlpga72 6x6 mm package. a. vfde feature can be enabled using dedicated pmbus command. see section 12 for details. figure 5. device initialization s vi p a cket vcc5 vdrv vin uvlo 2m s ec por uvlo uvlo 50 s ec en s vi bu s pmb us v_ s ingleph as e envtt s vrrdy v_m u ltiph as e vrrdy 64 s ec 64 s ec s vi p a cket comm a nd rejected comm a nd ack bu t not exec u ted am14 8 1 3 v1
output voltage positioning L6751 30/59 doc id 023992 rev 1 6 output voltage positioning output voltage positioning is performed by selecting the controller operative-mode, as per ta b l e 6 , for the two sections and by programming the droop function effect (see figure 6 ). the controller reads the current delivered by each section by monitoring the voltage drop across the dcr inductors. the current (i droop / i sdroop ) sourced from the fb / sfb pins, directly proportional to the read current, causes the related section output voltage to vary according to the external r fb / r sfb resistor, therefore implementing the desired load-line effect. the L6751 embeds a dual remote-sense buffer to sense remotely the regulated voltage of each section without any additional external components. in this way, the output voltage programmed is regulated compensating for board and socket losses. keeping the sense traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. figure 6. voltage positioning 6.1 multi-phase section - phase # programming the multi-phase section implements a flexible 3 to 6 interleaved-phase converter. to pro- gram the desired number of phases, simply short to vcc5 the pwmx signal that is not required, according to ta b l e 7 . caution: for the disabled phase(s), the current reading pins need to be properly connected to avoid errors in current-sharing and voltage-positioning: csxp needs to be connected to the regulated output voltage while csxn needs to be connected to csxp through the same r g resistor used for the active phases. 6.2 multi-phase section - current reading and current sharing loop the L6751 embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the induc- tor element. the fully-differential current reading rejects noise and allows the sensing ele- ment to be placed in different locations without affecting measurement accuracy. the trans- ref. from dac fb comp v s en fbr r f c f r fb to vddcore (remote s en s e) i droop protection monitor rgnd am14 8 14v1
L6751 output voltage positioning doc id 023992 rev 1 31/59 conductance ratio is issued by the external resistor r g placed outside the chip between the csxn pin toward the reading points. the current sense circuit always tracks the current information; the csxp pin is used as a reference keeping the csxn pin to this voltage. to correctly reproduce the inductor current, an r-c filtering network must be introduced in par- allel to the sensing element. the current that flows from the csxn pin is then given by the following equation (see figure 7 ): equation 2 considering now the matching of the time constant between the inductor and the r-c filter applied (time constant mismatches cause the introduction of poles into the current reading network causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: equation 3 figure 7. current reading the current read through the csxp / csxn pairs is converted into a current i infox propor- tional to the current delivered by each phase and the information about the average current i avg = i infox / n is internally built into the device (n is the number of working phases). the error between the read current i infox and the reference i avg is then converted into a voltage that, with a proper gain, is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. 6.3 multi-phase section - defining load-line the L6751 introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a depen- dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current. figure 7 shows the current sense circuit used to implement the load-line. the current flow- ing across the inductor(s) is read through the r-c filter across the csxp and csxn pins. r g i csxn dcr r g ------------- 1s l dcr ? ? + 1s r c ?? + ------------------------------------------- - i ? phasex ? = l dcr ------------- rc i csxn r l r g ------- - i phasex ? = ? ? i infox == lx c s xp c s xn dcr x r c r g i pha s ex ind u ctor dcr c u rrent s en s e i c s xn =i infox v out am14815v1
output voltage positioning L6751 32/59 doc id 023992 rev 1 programs a trans-conductance gain and generates a current i csx proportional to the current of the phase. the sum of the i csx current, with proper gain eventually adjusted by the pmbus commands, is then sourced by the fb pin (i droop ). r fb gives the final gain to pro- gram the desired load-line slope ( figure 6 ). time constant matching between the inductor (l / dcr) and the current reading filter (rc) is required to implement a real equivalent output impedance of the system, therefore avoid- ing over and/or undershoot of the output voltage as a consequence of a load transient. the output voltage characteristic vs. load current is then given by: equation 4 where r ll is the resulting load-line resistance implemented by the multi-phase section. the r fb resistor can be then designed according to the r ll specifications as follows: equation 5 caution: when in ddr mode, and enabled, droop current has a scaling factor equal to 1/4. all the above equations must be scaled accordingly. 6.4 single-phase section - disable the single-phase section can be disabled by pulling high the spwm pin. the related command is rejected. 6.5 single-phase section - current reading the single-phase section performs the same differential current reading across dcr as the multi-phase section. according to section 6.2 , the current that flows from the scsn pin is then given by the following equation (see figure 7 ): equation 6 6.6 single-phase section - defining load-line this method introduces a dependence of the output voltage on the load current recovering part of the drop due to the output capacitor esr in the load transient. introducing a depen- dence of the output voltage on the load current, a static error, proportional to the output cur- rent, causes the output voltage to vary according to the sensed current. v out vid r fb i droop ? ? vid r fb dcr r g ------------- i out ?? ? vid r ll i out ? ? == = r fb r ll r g dcr ------------- ? = i scsn dcr r sg ------------ - i sout ? i sdroop ==
L6751 output voltage positioning doc id 023992 rev 1 33/59 figure 7 shows the current sense circuit used to implement the load-line. the current flow- ing across the inductor dcr is read through r sg . r sg programs a trans-conductance gain and generates a current i sdroop proportional to the current delivered by the single-phase section that is then sourced from the sfb pin with proper gain eventually adjusted by the pmbus commands. r sfb gives the final gain to program the desired load-line slope ( figure 6 ). the output characteristic vs. load current is then given by: equation 7 where r sll is the resulting load-line resistance implemented by the single-phase section. the r sfb resistor can then be designed according to the r sll as follows: equation 8 6.7 dynamic vid transition support the L6751 manages dynamic vid transitions that allow the output voltage of both sections to be modified during normal device operation for power management purposes. ov, uv and oc signals are masked during every dvid transition and they are re-activated with proper delay to prevent from false triggering. when changing dynamically the regulated voltage (dvid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i dvid needs to be delivered (especially when increasing the output regulated voltage) and it must be con- sidered when setting the overcurrent threshold of both sections. this current results: equation 9 where dv out / dt vid depends on the specific command issued (20 mv/ sec for setvid_fast and 5 mv/ sec for setvid_slow). overcoming the total oc threshold during the dynamic vid causes the device to latch and disable. set proper filtering on ilim to pre- vent from false total-oc tripping. as soon as the controller receives a new valid command to set the vid level for one (or both) of the two sections, the reference of the involved section steps up or down according to the target-vid with the programmed slope until the new code is reached. if a new valid command is issued during the transition, the device updates the target-vid level and performs the dynamic transition up to the new code. ov, uv are masked during the transition and re-activated with proper delay after the end of the transition to prevent from false triggering. v sout =vid r sfb i sdroop ? ? vid r sfb dcr r sg ------------- i sout ?? ? vid r sll i sout ? ? = r sfb r sll r sg dcr ------------- ? = i dvid c out dv out dt vid ----------------- - ? =
output voltage positioning L6751 34/59 doc id 023992 rev 1 6.7.1 lsless startup and pre-bias output any time the device resumes from an ?off? code and at the first power-up, in order to avoid any kind of negative undershoot on the load side, the L6751 performs a special sequence in enabling the drivers: during the soft-start phase, the ls driver results as being disabled (ls=off - pwmx set to hiz and endrv = 0) until the first pwm pulse. after the first pwm pulse, pwmx outputs switch between logic ?0? and logic ?1? and endrv is set to logic ?1?. this particular sequence avoids the dangerous negative spike on the output voltage that can occur if starting over a pre-biased output. low-side mosfet turn-on is masked only from the control loop point of view: protection is still allowed to turn on the low-side mosfet if overvoltage is needed. 6.8 dvid optimization: ref/sref high slew rate for dynamic vid transitions causes undershoot on the regulated voltage, causing violation in the microprocessor requirement. to compensate this behavior and to remove any undershoot in the transition, each section features a dvid optimization circuit. the reference used for the regulation is available on the ref/sref pin (see figure 10 ). connect an r ref /c ref to gnd (r sref /c sref for the single-phase) to optimize the dvid behavior. components may be designed as follows (multi-phase, the same equations apply to single-phase): equation 10 where vosc is the pwm ramp and k v the gain for the voltage loop (see section 11 ). during a falling dvid transition, the ref pin moves according to the dvid command issued; the current requested to charge/discharge the r ref /c ref network is mirrored and added to the droop current compensating for undershoot on the regulated voltage. figure 8. lsless startup: enabled (left) figure 9. lsless startup: disabled (right) c ref c f 1 v osc k v v in ? ---------------------- ? ?? ?? ? = r ref r f c f ? c ref --------------------- - =
L6751 output voltage positioning doc id 023992 rev 1 35/59 figure 10. dvid optimization circuit ref ref r ref c ref ref fb comp v s en r f c f r fb z f ( s ) z fb ( s ) i droop v comp fbr to vddcore (remote s en s e) rgnd ref. from dac am14 8 17v1
output voltage monitoring and protection L6751 36/59 doc id 023992 rev 1 7 output voltage monitoring and protection the L6751 monitors the regulated voltage of both sections through pin vsen and svsen in order to manage ov and uv. the device shows different thresholds when in different opera- tive conditions but the behavior in response to a protection event is still the same as described below. protection is active also during soft-start while it is properly masked during dvid transitions with an additional delay to avoid false triggering. ov protection is active during dvid with threshold modified to 1.8 v unless offset has been commanded by svi or pmbus: in this case the fixed threshold is 2.4 v. table 13. L6751 protection at a glance 7.1 overvoltage when the voltage sensed by vsen and/or svsen surpasses the ov threshold, the control- ler acts in order to protect the load from excessive voltage levels avoiding any possible undershoot. to reach this target, a special sequence is performed as per the following list: ? the reference performs a dvid transition down to 250 mv on the section which triggered the ov protection. ? the pwms of the section which triggered the protection are switched between hiz and zero (endrv is kept high) in order to follow the voltage imposed by the dvid on-going. this limits the output voltage excursion, protects the load and assures no undershoot is generated (if vout < 250 mv, the section is hiz). ? the pwms of the non-involved section are set permanently to hiz (endrv is kept low) in order to realize a hiz condition. ? osc/ flt pin is driven high. ? power supply or en pin cycling is required to restart operation. if the cause of the failure is removed, the converter ends the transition with all pwms in hiz state and the output voltage of the section which triggered the protection lower than 250 mv. section multi-phase single-phase overvoltage (ov) vsen, svsen = +175 mv above reference. action: ic latch; ls = on & pwmx = 0 (if applicable); other section: hiz.vr_ready of the latched section resets (only). undervoltage (uv) vsen, svsen = 400 mv below reference. active after ref > 500 mv. action: ic latch; both sections hiz. vr_ready of the latched section resets (only). overcurrent (oc) current monitor across inductor dcr. dual protection, per-phase and total. action: uv-like. vr_ready of the latched section resets (only). dynamic vid protection masked with additional delay to prevent from false triggering.
L6751 output voltage monitoring and protection doc id 023992 rev 1 37/59 7.2 overcurrent and current monitor the overcurrent threshold must be programmed to a safe value, in order to be sure that each section does not enter oc during normal operation of the device. this value must take into consideration also the process spread and temperature variations of the sensing ele- ments (inductor dcr). furthermore, since also the internal threshold spreads, the design must consider the mini- mum/maximum values of the threshold. 7.2.1 multi-phase section the L6751 features two independent load indicator signals, imon and ilim, to properly manage oc protection, current monitoring and dpm. both imon and ilim source a current proportional to the current delivered by the regulator, as follows: equation 11 the imon and ilim pins are connected to gnd through a resistor (r imon and r ilim respec- tively), implementing a load indicator with different targets. imon is used for current reporting purposes and for the dpm phase shedding. r imon must be designed considering that i max must correspond to 1.24 v (for correct imax detection). ilim is used for the overcurrent protection only. r ilim must be designed considering that the oc protection is triggered when v(ilim)= 2.5 v. in addition, the L6751 also performs per-phase oc protection. ? per-phase oc. maximum information current per-phase (i infox ) is internally limited to 35 a. this end-of-scale current (i oc_th ) is compared with the information current generated for each phase (i infox ). if the current information for the single-phase exceeds the end-of-scale current (i.e. if i infox > i oc_th ), the device turns on the ls mosfet until the threshold is re-crossed (i.e. until i infox < i oc_th ). ? total current oc. the ilim pin allows a maximum total output current for the system (i oc_tot ) to be defined. ilim current is sourced from the ilim pin. by connecting a resistor r ilim to gnd, a load indicator with 2.5 v (v oc_tot ) end-of- scale can be implemented. when the voltage present at the ilim pin crosses v oc_tot , the device detects an oc and immediately latches with all the mosfets of all the sections off (hiz). typical design considers the intervention of the total current oc before the per-phase oc, leaving this last one as an extreme-protection in case of hardware failures in the external components. per-phase oc depends on the r g design while total oc is dependant on the ilim design and on the application tdc and max. current supported. typical design flow is the following: ? define the maximum total output current (i oc_tot ) according to system requirements (i max , i tdc ). considering i mon design, i max must correspond to 1.24 v (for correct imax detection) while considering ilim design i oc_tot must correspond to 2.5 v. ? design per-phase oc and r g resistor in order to have i infox = i oc_th (35 a) when i out is about 10% higher than the i oc_tot current. it results: i mon i lim dcr r g ------------- i out ? ==
output voltage monitoring and protection L6751 38/59 doc id 023992 rev 1 equation 12 where n is the number of phases and dcr the dc resistance of the inductors. r g should be designed in worst-case conditions. ? design the r imon in order to have the imon pin voltage to 1.24 v at the i max current specified by the design. it results: equation 13 where i max is max. current requested by the processor (see intel docs for details). ? design the r ilim in order to have the ilim pin voltage to 2.5 v at the i oc_tot current specified above. it results: equation 14 where i oc_tot is the overcurrent switch-over threshold previously defined. ? adjust the defined values according to application bench testing. ?c ilim in parallel to r ilim can be added with proper time constant to prevent false oc tripping and/or delay. ?c imon in parallel to r imon can be added to adjust the averaging interval for the current reporting and/or adjust the dpm latencies. additionally, it can be increased to prevent false total-oc tripping during dvid. note: this is the typical design flow. custom design and specifications may require different settings and ratios between the per-phase oc threshold and the total current oc threshold. applications with big ripple across inductors may be required to set per-phase oc to values different than 110%: design flow should be modified accordingly. current reporting precision on imon may be affected by external layout. the internal adc is referenced to the device gnd pin: in order to perform the highest accuracy in the current monitor, r imon must be routed to the gnd pin with dedicated net to avoid gnd plane drops affecting the precision of the measurement. 7.2.2 overcurrent and power states when the controller receives an setps command through the svi interface, it automatically changes the number of working phases. in particular, the maximum number of phases which L6751 may work in >ps00h is limited to 2 phases regardless of the number n configured in ps00h. oc level is then scaled as the controller enters >ps00h, as per ta bl e 1 4 . r g 1.1 i oc_tot ? () dcr ? ni ? octh ------------------------------------------------------------- - = r imon 1.24v r g ? i max dcr ? --------------------------------- = r ilim 2.5v r g ? i oc_tot dcr ? ----------------------------------------- =
L6751 output voltage monitoring and protection doc id 023992 rev 1 39/59 7.2.3 single-phase section the L6751 performs two different kinds of oc protection for the single-phase section: it monitors both the total current and the per-phase current and allows an oc threshold to be set for both. ? per-phase oc. maximum information current per-phase (i sinfox ) is internally limited to 35 a. this end-of-scale current (i soc_th ) is compared with the information current generated for each phase (i sinfox ). if the current information for the single-phase exceeds the end-of-scale current (i.e. if i sinfox > i soc_th ), the device turns on the ls mosfet until the threshold is re-crossed (i.e. until i sinfox < i soc_th ). ? total current oc. the simon pin allows a maximum total output current for the system (i soc_tot ) to be defined. i smon current is sourced from the simon pin. by connecting a resistor r simon to gnd, a load indicator with 1.55 v (v soc_tot ) end- of-scale can be implemented. when the voltage present at the simon pin crosses v soc_tot , the device detects an oc and immediately latches with all the mosfets of all the sections off (hiz). typical design considers the intervention of the total current oc before the per-phase oc, leaving this last one as an extreme protection in case of hardware failures in the external components. total current oc is, moreover, dependant on the simon design and on the application tdc and max current supported. typical design flow is the following: ? define the maximum total output current (i soc_tot ) according to system requirements (i smax , i stdc ). considering i smon design, i smax must correspond to 1.24 v (for correct simax detection) so i soc_tot results defined, as a consequence, as ? design per-phase oc and r sg resistor in order to have i sinfox = i soc_th (35 a) when i sout is about 10% higher than the i soc_tot current. it results: equation 15 where dcr is the dc resistance of the inductors. r sg should be designed in worst-case conditions. ? design the total current oc and r simon in order to have the simon pin voltage to 1.24 v at the i smax current specified by the design. it results: table 14. multi-phase section oc scaling and power states power state [hex] n oc level (v oc_tot ) 00h 3 to 6 2.500 v 01h, 02h 3 1.650 v 4 1.250 v 5 1.000 v 6 0.830 v i soc_tot i smax 1.55 ? 1.24 ? = r sg 1.1 i soc_tot ? () dcr ? i socth ----------------------------------------------------------------- =
output voltage monitoring and protection L6751 40/59 doc id 023992 rev 1 equation 16 where i smax is max. current requested by the processor (see intel docs for details). ? adjust the defined values according to application bench tests. ?c simon in parallel to r simon can be added with proper time constant to prevent false oc tripping. note: this is the typical design flow. custom design and specifications may require different settings and ratios between the per-phase oc threshold and the total current oc threshold. applications with big ripple across inductors may be required to set per-phase oc to values different than 110%: design flow should be modified accordingly. r simon 1.24v r sg ? i smax dcr ? ------------------------------------ - = i simon dcr r sg ------------- i sout ? = ?? ??
L6751 single ntc thermal monitor and compensation doc id 023992 rev 1 41/59 8 single ntc thermal monitor and compensation the L6751 features single ntc for thermal sensing for both thermal monitoring and compensation. thermal monitor consists in monitoring the converter temperature eventually reporting alarm by asserting the vr_hot signal. this is the base for the temperature reporting. thermal compensation consists in compensating the inductor dcr derating with temperature, so preventing drifts in any variable correlated to the dcr: voltage positioning, overcurrent (ilim), imon, current reporting. both the functions share the same thermal sensor (ntc) to optimize the overall application costs without compromising performance. the thermal monitor is featured for both single-phase and multi-phase sections. 8.1 thermal monitor and vr_hot the diagram for the thermal monitor is reported in figure 11 . ntc should be placed close to the power stage hot-spot in order to sense the regulator temperature. as the temperature of the power stage increases, the ntc resistive value decreases, therefore reducing the voltage observable at the tm/stm pin. recommended ntc is nths0805n02n6801he for accurate temperature sensing and thermal compensation. different ntc may be used: to reach the requested accuracy in temperature reporting, the proper resistive network must be used in order to match the resulting characteristic with the one coming from the recommended ntc. the voltage observed at the tm/stm pin is internally converted and then used for the temperature reporting. when the temperature observed on one of the two thermal sensors exceeds tmax (programmed via pinstrapping), the L6751 asserts vr_hot (active low - as long as the overtemperature event lasts). figure 11. thermal monitor connections 8.2 thermal compensation the L6751 supports dcr sensing for output voltage positioning: the same current information used for voltage positioning is used to define the overcurrent protection and the current reporting. having imprecise and temperature-dependant information leads to violation of the specification and misleading information: positive thermal coefficient specific from dcr needs to be compensated to get stable behavior of the converter as temperature vcc5 tm temperature decoding vr_hot temp. zone 2k ntc am14 8 1 8 v1
single ntc thermal monitor and compensation L6751 42/59 doc id 023992 rev 1 increases. un-compensated systems show temperature dependencies on the regulated voltage, overcurrent protection and current reporting. the temperature information available on the tm/stm pin and used for thermal monitoring may be used also for this purpose. by comparing the voltage on the tm/stm pin with the voltage present on the tcomp/stcomp pin, the L6751 corrects the i droop /i sdroop current used for voltage positioning (see section 6.3 ), so recovering the dcr temperature deviation. depending on ntc location and distance from the inductors and the available airflow, the correlation between ntc temperature and dcr temperature may be different: tcomp/stcomp adjustments allow the gain between the sensed temperature and the correction made on the i droop /i sdroop current to be modified. short tcomp/stcomp to gnd to disable thermal compensation (no correction of i droop /i sdroop is made). 8.3 tm/stm and tcomp/stcomp design this procedure applies to both single-phase and multi-phase sections. 1. properly choose the resistive network to be connected to the tm pin. recommended values/network is reported in figure 11 . 2. connect voltage generator to the tcomp pin (default value 3.3 v). 3. power on the converter and load the thermal design current (tdc) with the desired cooling conditions. record the output voltage regulated as soon as the load is applied. 4. wait for thermal steady-state. adjust down the voltage generator on the tcomp pin in order to get the same output voltage recorded at point #3. 5. design the voltage divider connected to tcomp (between vcc5 and gnd) in order to get the same voltage set to tcomp at point #4. 6. repeat the test with the tcomp divider designed at point #5 and verify the thermal drift is acceptable. in the case of positive drift (i.e. output voltage at thermal steady- state is bigger than output voltage immediately after loading tdc current), change the divider at the tcomp pin in order to reduce the tcomp voltage. in the case of negative drift (i.e. output voltage at thermal steady-state is smaller than output voltage immediately after loading tdc current), change the divider at the tcomp pin in order to increase the tcomp voltage. 7. the same procedure can be implemented with a variable resistor in place of one of the resistors of the divider. in this case, once the compensated configuration is found, simply replace the variable resistor with a resistor with the same value.
L6751 efficiency optimization doc id 023992 rev 1 43/59 9 efficiency optimization as per vr12 specifications, the svi master may define different power states for the vr controller. this is performed by setps commands. the L6751 re-configures itself to improve overall system efficiency, according to ta bl e 1 5 . 9.1 dynamic phase management (dpm) dynamic phase management allows the number of working phases to be adjusted according to the delivered current still maintaining the benefits of the multi-phase regulation. phase number is reduced by monitoring the voltage level across the imon pin: the L6751 reduces the number of working phases according to the strategy defined by the dpm pinstrapping and/or pmbus (tm) commands received (see ta bl e 1 1 ). dpm12 refers to the current at which the controller changes from 1 to 2 phases. in the same way, dpm23 defines the current at which the controller changes from 2 to 3 phases and so on. when dpm is enabled, the L6751 starts monitoring the imon voltage for phase number modification after vr_rdy has transition high: the soft-start is then implemented in interleaving mode with all the available phases enabled. dpm is reset in the case of an setvid command that affects the core section and when ltb technology detects a load transient. after being reset, if the voltage across imon is compatible, dpm is re-enabled after proper delay. delay in the intervention of dpm can be adjusted by properly sizing the filter across the imon pin. increasing the capacitance results in increased delay in the dpm intervention. see section 7.2.1 for guidelines in designing the imon load indicator. note: during load transients with light slope, the filtering of imon may result too slow for the ic to set the correct number of phases required for the current effectively loading the system (ltb does not trigger in the case of light slopes). the L6751 features a safety mechanism which re-enables phases that were switched off by comparing ilim and imon pin voltage. in fact, the ilim pin is lightly filtered in order to perform fast reaction of oc protection while imon is heavily filtered to perform correct averaging of the information. while working continuously in dpm, the device compares the information of imon and ilim: ilim voltage is divided in n steps whose width is v ocp /(2*n) (where v ocp = 2.5 v and n the number of stuffed phases). if the dpm phase number resulting from imon is not coherent with the step in which ilim stays, the phase number is increased accordingly. the mechanism is active only to increase the phase number which is reduced again by dpm. table 15. efficiency optimization feature ps00h ps01h dpm according to pinstrapping active. 1phase/2phase according to iout vfde active when in single-phase and dpm enabled active when in single-phase gdc 12 v driving gdc set to 5 v
efficiency optimization L6751 44/59 doc id 023992 rev 1 9.2 variable frequency diode emulation (vfde) as the current required by the load is reduced, the L6751 progressively reduces the number of switching phases according to dpm settings on the multi-phase section. if single-phase operation is configured, when the delivered current approaches the ccm/dcm boundary, the controller enters vfde operation. the single-phase section, being a single-phase, enters vfde operation always when the delivered current approaches the ccm/dcm boundary. in a common single-phase dc-dc converter, the boundary between ccm and dcm is when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the inductor (iout = ipp/2). further decreasing the load in this condition maintaining ccm operation would cause the current into the inductor to reverse, therefore sinking current from the output for a part of the off-time. this results in a poorly efficient system. the L6751 is able (via the cspx/csnx pins) to detect the sign of the current across the inductor (zero cross detection, zcd), so it is able to recognize when the delivered current approaches the ccm/dcm boundary. in vfde operation, the controller fires the high-side mosfet for a ton and the low-side mosfet for a toff (the same as when the controller works in ccm mode) and waits the necessary time until next firing in high impedance (hiz). the consequence of this behavior is a linear reduction of the ?apparent? switching frequency that, in turn, results in an improvement of the efficiency of the converter when in very light load conditions. the ?apparent? switching frequency reduction is limited to 30 khz so as not to enter the audible range. 9.2.1 vfde and drmos to guarantee correct behavior for the drmos power stage compliant with intel specification rev3, it is recommended to control the drmos? smod input through the endrv/sendrv pins of the L6751. drmos enable must be controlled with the same signal used for the L6751 en pin. figure 12. output current vs. switching frequency in psk mode t io u t = ipp/2 t io u t < ipp/2 t s w t s w tvfde am14 8 19v1
L6751 efficiency optimization doc id 023992 rev 1 45/59 proper hiz level can be programmed by adding proper external resistor divider across pwm1 and pwm2. see section 4.2 for details about hiz level recognition. see reference schematic in figure 1 . 9.3 gate drive control (gdc) gate drive control (gdc) is a proprietary function which allows the L6751 to dynamically control the power mosfet driving voltage in order to further optimize the overall system efficiency. according to the svi power state commanded and the configuration received through the pmbus, the device switches this pin (gdc) between the vcc5 or vdrv (inputs). by connecting the power supply of external drivers directly to this pin, it is then possible to carefully control the external mosfet driving voltage. in fact, high driving voltages are required to obtain good efficiency in high loading conditions. on the contrary, in lower loading conditions, such high driving voltage penalizes efficiency because of high losses in qgs. gdc allows to tune the mosfet driving voltage according to the delivered current. the default configuration considers gdc always switched to vdrv except when entering power states higher than ps01h (included): in this case, to further increase efficiency, simply supply the phase1 and phase2 driver through the gdc pin. their driving voltage is automatically updated as lower power states are commanded through the svi interface. further optimization may be possible by properly setting the automatic gdc threshold through the dedicated pmbus command and/or pinstrapping. it is then possible to enable the gate driving voltage switchover even in ps00h. according to the positioning of the threshold compared with dpm thresholds, it is possible to achieve different performances. simulations and/or bench tests may be of help in defining the best performing configuration achievable with the active and passive components available. figure 13 allows the efficiency improvements with dpm/gdc enabled to be compared with respect to the standard solution. note: systems supporting s3 power state may have the vdrv supplied by an or-ing connection between 5 vsby and 12 v or different supply voltage for s0. it is recommended to connect closely, between the vdrv and vcc5 pins, the or-ing diode connecting vdrv to the 5 vsby. figure 13. efficiency performance with and without enhancements (dpm, gdc)
main oscillator L6751 46/59 doc id 023992 rev 1 10 main oscillator the internal oscillator generates the triangular waveform for the pwm charging and discharging, with a constant current, on the internal capacitor. the switching frequency for each channel is internally fixed at 200 khz (f sw ) and at 230 khz (f ssw ): the resulting switching frequency at the load side for the multi-phase section results in being multiplied by n (number of configured phases). the current delivered to the oscillator is typically 20 a and may be varied using an external resistor (r osc , r sosc ) typically connected between the osc/sosc pins and gnd. since the osc/sosc pins are fixed at 1.02 v, the frequency is varied proportionally to the current sunk from the pin considering the internal gain of 10 khz/ a for the multi-phase section and of 11.5 khz/ a for the single-phase section, see figure 14 . connecting r osc /r sosc to sgnd, the frequency is increased (current is sunk from the pin), according to the following relationships: equation 17 equation 18 connecting r osc /r sosc to a positive voltage vbias, the frequency is reduced (current is injected into the pin), according to the following relationships: equation 19 equation 20 figure 14. r osc vs. f sw per phase (r osc to gnd - left; r osc to 3.3 v - right) f sw 200khz 1.02v r osc k () --------------------------- 10 khz a ---------- - ? + = f ssw 250khz 1.02v r sosc k () ------------------------------ - 11.5 khz a ---------- - ? + = f sw 200khz vbias 1.02v ? r osc k () ------------------------------------- - 10 khz a ---------- - ? ? = f ssw 250khz vbias 1.02v ? r sosc k () ------------------------------------- - 11.5 khz a ---------- - ? ? = 10 100 1000 200 3 00 400 500 600 700 8 00 900 1000 m u lti ph as e s ection s ingleph as e s ection 100 1000 75 100 125 150 175 200 225 m u lti ph as e s ection s ingleph as e s ection am14 8 20v1
L6751 system control loop compensation doc id 023992 rev 1 47/59 11 system control loop compensation the control system can be modeled with an equivalent single-phase converter with the only difference being the equivalent inductor l/n (where each phase has an l inductor and n is the number of the configured phases), see figure 15 . figure 15. equivalent control loop. the control loop gain results (obtained opening the loop after the comp pin): equation 21 where: r ll is the equivalent output resistance determined by the droop function (voltage positioning) z p (s) is the impedance resulting from the parallel of the output capacitor (and its esr) and the applied load r o z f (s) is the compensation network impedance z l (s) is the equivalent inductor impedance a(s) is the error amplifier gain is the pwm transfer function. the control loop gain is designed in order to obtain a high dc gain to minimize static error and to cross the 0 db axes with a constant -20 db/dec slope with the desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. ref fb comp v s en r f c f r fb pwm l/n e s r c o r o d v comp v out z f ( s ) z fb ( s ) i droop v comp fbr rgnd am14 8 21v1 g loop s () pwm z f s () r ll z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------------ - ? = pwm 9 10 ------ v in v osc ------------------ - ? =
system control loop compensation L6751 48/59 doc id 023992 rev 1 figure 16. control loop bode diagram and fine tuning to obtain the desired shape, an r f -c f series network is considered for the z f (s) implementation. a zero at f =1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance and assures a simple -20 db/dec shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results as being at a frequency lower than the above reported zero. the compensation network can be designed as follows: equation 22 equation 23 11.1 compensation network guidelines the compensation network design assures a system response according to the crossover frequency selected and to the output filter considered: it is however possible to further fine tune the compensation network by modifying the bandwidth in order to get the best response of the system as follows (see figure 16 ): ? increase r f to increase the system bandwidth accordingly. ? decrease r f to decrease the system bandwidth accordingly. ? increase c f to move f to low frequencies, increasing as a consequence the system phase margin. having the fastest compensation network does not guarantee that the load requirements are satisfied: the inductor still limits the maximum di/dt that the system can afford. in fact, when a load transient is applied, the best that the controller can do is to ?saturate? the duty cycle to its maximum (d max ) or minimum (0) value. the output voltage dv/dt is then limited by the inductor charge/discharge time and by the output capacitance. in particular, the most limiting transition corresponds to the load-removal since the inductor results as being discharged only by v out (while it is charged by v in -v out during a load appliance). db z f ( s ) g loop ( s ) k lc = f e s r t r f [db] db z f ( s ) g loop ( s ) k lc = f e s r t r f [db] r f c f am14 8 22v1 r f r fb v osc ? v in ------------------------------------ - 10 9 ------ f sw l ? r ll esr + () --------------------------------- - ?? = c f c o l ? r f ---------------------- - =
L6751 system control loop compensation doc id 023992 rev 1 49/59 note: the introduction of a capacitor (c i ) in parallel to r fb significantly speeds up the transient response by coupling the output voltage dv/dt on the fb pin, so using the error amplifier as a comparator. the comp pin suddenly reacts and, also thanks to the ltb technology control scheme, all the phases can be turned on together to immediately give the required energy to the output. typical design considers starting from values in the range of 100 pf, and validating the effect by bench testing. additional series resistor (r i ) can also be used. 11.2 ltb technology ltb technology further enhances the performance of the controller by reducing the system latencies and immediately turning on all the phases to provide the correct amount of energy to the load optimizing the output capacitor count. ltb technology monitors the output voltage through a dedicated pin detecting load- transients with selected dv/dt, it cancels the interleaved phase-shift, turning on simultaneously all phases. the ltb detector is able to detect output load transients by coupling the output voltage through an r lt b - c ltb network. after detecting a load transient, all the phases are turned on together and the ea latencies also result as bypassed. sensitivity of the load transient detector can be programmed in order to control precisely both the undershoot and the ring-back. ltb technology design tips. ? decrease r lt b to increase the system sensitivity making the system sensitive to smaller dv out ? increase c lt b to increase the system sensitivity making the system sensitive to higher dv/dt ? increase r i to increase the width of the ltb pulse ? increase c i to increase the ltb sensitivity over frequency.
pmbus support (preliminary) L6751 50/59 doc id 023992 rev 1 12 pmbus support (preliminary) the L6751 is compatible with pmbus? standard revision 1.1, refer to pmbus standard documentation for further information (www.pmbus.org). table 16. supported commands command per rail code [hex] mode comments operation y 01 rw byte used to turn the controller on/off in conjunction with the input from the control pin. also used to set margin voltages. soft off not supported on_off_config n 1 02 rw byte configures how the controller responds when power is applied write_protect y 10 rw byte controls writing to the pmbus device to prevent accidental changes vout_command y 21 rw word causes the converter to set its output voltage to the commanded value - vid mode vout_max y 24 rw word sets the upper limit on the output voltage regardless of any other command vout_margin_high y 25 rw word sets the voltage to which the output is to be changed when the operation command is set to ?margin high? vout_margin_low y 26 rw word sets the voltage to which the output is to be changed when the operation command is set to ?margin low? iout_cal_offset y 39 rw word calibration for iout reading ot_fault_limit y 4f rw word overtemperature fault threshold ot_warn_limit y 51 rw word overtemperature warning threshold vin_ov_fault_limit n 55 rw word input voltage monitor overvoltage limit vin_uv_fault_limit n 59 rw word input voltage monitor undervoltage limit mfr_specific_01 n d1 rw byte average_time_scale. sets the time between two measurements mfr_specific_02 y d2 rw byte debug_mode. [01/10] switches [on/off] the vout control on pmbus domain mfr_specific_05 y d5 rw byte vout_trim. used to apply a fixed offset voltage to the output voltage command value mfr_specific_08 y d8 rw byte vout_droop. used to change the vout droop mfr_specific_35 n 1 f3 rw byte manual_phase_shedding. used to manage the phase shedding manually mfr_specific_38 y f6 rw byte vout_ov_fault_limit. allows the ov protection threshold to be programmed for each rail mfr_specific_39 y f7 rw byte vfde_enable mfr_specific_40 y f8 rw byte ultrasonic_enable
L6751 pmbus support (preliminary) doc id 023992 rev 1 51/59 mfr_specific_41 n 1 f9 rw byte gdc_threshold. to access the internal register to set gdc threshold [a] mfr_specific_42 n 1 fa rw byte dpm12_threshold. to access the internal register to set the dpm12 threshold [a] mfr_specific_43 n 1 fb rw byte dpm23_threshold. to access the internal register to set the dpm23 threshold [a] mfr_specific_44 n 1 fc rw byte dpm34_threshold. to access the internal register to set the dpm34 threshold [a] mfr_specific_45 n 1 fd rw byte dpm46_threshold. to access the internal register to set the dpm46 threshold [a] capability n 19 r byte provides a way for a host system to determine key capabilities of a pmbus device, such as maximum bus speed and pmbus alert. vout_mode n 20 r byte the device operates in vid mode pmbus_revision n 98 r byte revision of the pmbus which the device is compliant to mfr_id n 99 r block returns the manufacturers id mfr_model n 9a r block returns manufacturers model number mfr_revision n 9b r block returns the device revision number mfr_specific_ext ended_command_ 00 y 00 r byte vr12_status1 mfr_specific_ext ended_command_ 01 y 01 r byte vr12_status2 mfr_specific_ext ended_command_ 02 y 02 r byte vr12_tempzone mfr_specific_ext ended_command_ 03 y 03 r byte vr12_iout mfr_specific_ext ended_command_ 05 y 05 r byte vr12_vrtemp mfr_specific_ext ended_command_ 07 y 07 r byte vr12_status2_lastread mfr_specific_ext ended_command_ 08 y 08 r byte vr12_iccmax mfr_specific_ext ended_command_ 09 y 09 r byte vr12_tempmax table 16. supported commands command per rail code [hex] mode comments
pmbus support (preliminary) L6751 52/59 doc id 023992 rev 1 mfr_specific_ext ended_command_ 10 y 0a r byte vr12_srfast mfr_specific_ext ended_command_ 11 y 0b r byte vr12_srslow mfr_specific_ext ended_command_ 12 y 0c r byte vr12_vboot mfr_specific_ext ended_command_ 13 y 0d r byte vr12_voutmax mfr_specific_ext ended_command_ 14 y 0e r byte vr12_vidsetting mfr_specific_ext ended_command_ 15 y 0f r byte vr12_pwrstate mfr_specific_ext ended_command_ 16 y 10 r byte vr12_offset clear_faults n 03 send byte used to clear any fault bits that have been set read_vin n 88 r word returns the input voltage in volts (vin pin) read_vout y 8b r word returns the actual reference used for the regulation in vid format read_iout y 8c r word returns the output current in amps read_duty_cycle n 1 94 r word returns the duty cycle of the devices main power converter in percentage mfr_specific_04 y d4 r word read_vout. returns the actual reference used for the regulation in volts for linear format read_temperatur e_1 y 8d r word read_temperature. [degc] status_byte y 78 r byte one byte with information on the most critical faults status_word y 79 r word two bytes with information on the units fault condition status_vout y 7a r byte status information on the output voltage warnings and faults status_iout y 7b r byte status information on the output current warnings and faults status_temperatu re y 7d r byte status information on the temperature warnings and faults status_cml y 7e r byte status information on the units communication, logic and memory table 16. supported commands command per rail code [hex] mode comments
L6751 pmbus support (preliminary) doc id 023992 rev 1 53/59 note: 1 applies to multi-phase only. 2 applies to single-phase only. 12.1 enabling the device through pmbus the default condition for the L6751 is to power up through the en pin ignoring pmbus commands. by properly setting the on_off_config command, it is also possible to let the device ignore the en pin acting only as a consequence of the operation command issued. 12.2 controlling vout through pmbus vout can be set independently from setvid commands issued through the svi interface by using pmbus. two main modes can be identified as: ? offset above svi commanded voltage. by enabling the margin mode through the operation command and by commanding the margin_high and margin_low registers, it is possible to dynamically control an offset above the output voltage commanded through the svi bus. ? fixed vout regardless of svi. it is necessary to enter debug_mode. in this condition, commands from svi are acknowledged but not executed and vout_command controls the voltage regulated on the output. the L6751 can enter and exit debug_mode anytime. upon any transition, vout remains un- changed and only the next-coming command affects the output voltage positioning (i.e. when exiting debug_mode, returning to svi domain, output voltage remains unchanged until the next setvid command). status_input n 1 7c r byte status information on the input warning and fault status_mfr_speci fic y 80 r byte manufacturer specific status table 16. supported commands command per rail code [hex] mode comments
pmbus support (preliminary) L6751 54/59 doc id 023992 rev 1 12.3 input voltage monitoring (read_vin) the dedicated pmbus command allows the user to monitor input voltage. by connecting the vin pin to the input voltage with the recommended resistor values, the L6751 returns the value of the input voltage measured as a voltage (linear format, n=-4). the divider needs to be programmed to have 1.24 v on the pin when vin=15.9375 v. according to this, r up =118.5 k and r down =10 k . errors in defining the divider lead to monitoring errors accordingly. filter vin pin locally to gnd to increase stability of the voltage being measured. 12.4 duty cycle monitoring (read_duty) the dedicated pmbus command allows the user to monitor duty cycle for multi-phase with the aim of calculating input current inexpensively (no need for input current-sense resistors). by connecting the phase pin to the phase1 phase pin, the L6751 returns the value of the duty cycle as a percentage (linear format, n=-2). the divider needs to be programmed to respect absolute maximum ratings for the pin (7 vmax). according to this, r up =5.6 k and r down =470 . figure 17. device initialization: pmbus controlling vout vcc5 vdrv vin uvlo 2m s ec por uvlo uvlo 50 s ec en s vi bu s pmb us v_ s ingleph as e envtt (ignored b y on_off_config s etting) s vrrdy 64 s ec on-off_config oper a tion v_m u ltiph as e vrrdy 64 s ec s vi p a cket comm a nd rejected comm a nd ack bu t not exec u ted am14 8 2 3 v1
L6751 pmbus support (preliminary) doc id 023992 rev 1 55/59 12.5 output voltage monitoring (read_vout) the dedicated pmbus command allows the user to monitor output voltage for both sections. the L6751 returns the value of the programmed vid in vid lsbs (i.e. number of lsbs. c8h = 200 dec x 5 mv = 1.000 v). 12.6 output current monitoring (read_iout) the dedicated pmbus command allows the user to monitor output current for both sections. the L6751 returns the value of the delivered current by reading imon voltage (same as vr12 register 15h) in amperes (linear format, n=0). 12.7 temperature monitoring (read_temperature) the dedicated pmbus command allows the user to monitor the temperature of the power section for multi-phase. the L6751 returns the value of the temperature sensed by ntc connected on the tm/stm pin (the same as vr12 temperature zone) in degrees celsius (linear format, n=0). 12.8 overvoltage threshold setting the dedicated mfr_specific command allows the user to program specific thresholds for multi-phase and single-phase sections. the threshold can be programmed according to ta b l e 1 7 . different thresholds can be configured for multi-phase and single-phase sections. this product is subject to a limited license from power-one ? . related to digital power technology patents owned by power-one. this license does not extend to standalone power supply products. table 17. ov threshold setting data byte [hex] oc threshold [mv] (above programmed vid) 00h +175 mv (default) 01h +225 mv 02h +275 mv 03h +325 mv
package mechanical data L6751 56/59 doc id 023992 rev 1 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 18. L6751 wplga72 6x6 mm mechanical data dim. mm min. typ. max. a 0.60 0.70 0.80 a1 0.005 0.025 0.045 d6.00 d2 3.55 3.60 3.65 e6.00 e2 3.55 3.60 3.65 b 0.25 0.30 0.35 b1 0.20 0.25 0.30 e1 0.5 e2 0.55 k 0.20 0.25 0.30 l1 0.05 0.15 aaa 0.15 bbb 0.10 ddd 0.05 eee 0.08 fff 0.10 ccc 0.10
L6751 package mechanical data doc id 023992 rev 1 57/59 figure 18. L6751 wplga72 6x6 mm package dimensions a 1 c b a d
revision history L6751 58/59 doc id 023992 rev 1 14 revision history table 19. document revision history date revision changes 29-nov-2012 1 initial release.
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